1. Field of the Invention
This invention relates to the manufacture of integrated circuit devices. More particularly, this invention relates to an improved method for forming sloped interconnects or vias between conducting layers separated by insulating layers.
2. Description of the Prior Art
Conducting layers, separated by insulating layers in an integrated circuit device, are electrically connected together using interconnects or vias which pass through the insulating layer. In its simplest form, such a via may be formed by first masking the insulating layer with photoresist and then selectively etching a portion of the insulating layer, through an opening formed in the photoresist using well known photolithographic techniques, to form an opening to the underlying conducting layer. An anisotropic etch may be used to form a hole having the same size as the opening in the photoresist or an isotropic etch may be used to provide a larger opening through undercutting of the photoresist mask opening.
After etching the opening, the photoresist layer is removed and a layer of conducting material, such as aluminum, is then deposited over the insulating layer. The conducting material also deposits in the via to form the electrical interconnect between the conducting layers.
While this method of forming a via is satisfactory when the opening is sufficiently large and the insulating layer is thin, complications can arise when a thicker insulating layer and/or a smaller size via is formed. The use of a thick insulating layer, while preferred from the standpoint of lower capacitance between conducting layers, results in the formation of a larger step as well as unacceptable thinning of the conducting layer adjacent the edge of the via. Smaller size vias, while desirable to decrease via pitch, can result in incomplete filling of the via with conducting material causing formation of voids or defects.
Previous attempts to prevent such problems from occurring included the use of a sloped sidewall via; for example, by the use of an etch capable of attacking the insulating layer/photoresist interface; or, for example, by the use of a layer between the insulating layer and the photoresist layer comprising a material capable of etching faster than the insulating material.
Oversize vias have been used in the prior art for defect protection. Typically, an opening conforming to the desired size of the via is etched through the insulating layer and then a second layer of insulating material is applied over the first layer. The second insulating layer is then masked and anisotropically etched to form a larger via generally in registry with the smaller via underneath. The amount of etching is controlled to remove only an amount of insulating material generally conforming to the amount deposited to form the second insulating layer, both to control the depth of the oversized via as well as to remove from the bottom of the smaller underlying via any insulating material deposited during formation of the second insulating layer.
The use of a thick insulating layer, or multiple insulating layers, however, can also result in the formation of larger steps. This can result in the need for planarization of the insulating layer prior to deposition of a conducting layer thereon. Gwozdz U.S. Pat. No. 4,451,326, assigned to the assignee of this invention, describes and claims a method for planarization wherein a sufficient amount of photoresist is deposited over an insulating layer having steps therein to fill in the low spots. The layers are then etched using an etchant which will remove both photoresist and the insulating material at about the same rate. This results in the removal of insulating material from the high spots while photoresist is removed from the low areas to thus smooth out the step upon subsequent removal of the photoresist material.
Thomas et al U.S. Pat. No. 4,481,070, also assigned to the assignee of this invention, describes and claims a double planarization method wherein a first insulating layer is planarized and a second insulating layer is then applied over the first layer and then also planarized.
While such prior art approaches to via construction included solutions to some of the problems encountered, unfortunately other problems were sometimes created by such solutions. For example, the formation of sloped vias in the prior art suffers from variable growth in via size. This is due to a combination in the variation in the slope angle of from 30 to 60 degrees and the need to overetch to assure completion of the etch in spite of manufacturing variations. For example, if the slope angle is 30 degrees, and the amount of overetch is 14%, the amount of growth in the via size can be shown to be 49% of the thickness of the insulating layer.
When planarization techniques, such as described above, are utilized, thickness of the insulating layer may vary over a wider range, thus further expanding the range of possible via size when forming sloped vias. For example, a typical 1 micron thick insulating layer may actually vary in thickness from 0.9 to 1.1 microns. With planarization, however, typical deposition thicknesses are 2.0 microns, typical resist thickness is 1.0 micron with 5% random variation, and typical planarization etches are performed with 10% random variation to leave 1.0 micron of insulating material. Therefore, with planarization, the range of thickness of the insulating layer, calculated by taking the square root of the squares of the independent variables, will be from 0.7 to 1.3 microns.
Furthermore, as the size of the integrated circuit devices continue to decrease and the density of the integration continues to increase, the use of many vias requires decreasing the via pitch to space the vias as close together as possible. Via pitch is defined as the via separation plus via size. Generally via size and via size tolerance enter the design consideration in such a way that larger vias and larger via tolerance both increase pitch. Hence the increased via sizes and increased tolerances due to prior art planarization and slope etching techniques lead to increased pitch and therefore a disadvantage.
Thus in the prior art, the formation of vias without the use of slopes or oversize vias could result in the formation of voids or trenches, as well as step coverage problems if a thick insulating layer is used; while higher capacitance can result from the use of a thinner insulating layer. When sloped vias or oversized vias are used, via pitch is negatively impacted, particularly if planarization techniques are also used to reduce the step formation.